发明名称 Multi-level voltage regulator system
摘要 A multi-level voltage regulator system/method providing discrete regulation of a DC-DC intermediate bus converter (IBC) output voltage (Vout) is disclosed. The disclosed system/method allows IBC Vout to be regulated in discrete steps during periods where IBC input voltage (Vin) falls below nominal operating values. Rather than shutting down or degrading IBC Vout in an unpredictable non-linear fashion based on IBC input/loading, IBC Vout is regulated in fixed discrete steps, allowing IBC-connected point-of-load (POL) converters to obtain stable power input that is well-defined over IBC Vin. IBC operating parameters may define multi-dimensional operational state spaces of IBC Vout regulation that ensure optimum power flow to attached POLs while maintaining operational stability within the IBC regulator. Instabilities in IBC/POL performance across variations in IBC Vin, load transients, POL loading, and environmental variables may be prevented using Vin voltage step hysteresis.
申请公布号 US9520772(B2) 申请公布日期 2016.12.13
申请号 US201313968955 申请日期 2013.08.16
申请人 TDK-LAMBDA CORPORATION 发明人 He Jin;Boylan Jeffrey John
分类号 H02M3/04;G05F1/10;H02M3/337;H02M3/335;H02M1/00 主分类号 H02M3/04
代理机构 Carstens & Cahoon, LLP 代理人 Carstens David W.;Klughart Kevin M.;Carstens & Cahoon, LLP
主权项 1. A multi-level voltage regulator system comprising: (a) input voltage detector (IVD); (b) voltage source reference (VSR); (c) regulation feedback comparator (RFC); and (d) intermediate bus DC-DC converter (IBC); wherein said RFC comprises a positive input node, a negative input node, and a comparison output node; said IBC comprises a voltage bus input port (VBIP), voltage bus output port (VBOP), and voltage adjust input port (VAIP); said RFC positive input node is electrically coupled to said VSR; said RFC negative input node is electrically coupled to said VBOP; said RFC comparison output node is electrically coupled to said VAIP; said IVD is configured to monitor said VBIP and generate a stepped reference voltage (SRV) to the voltage detected at said VBIP; said SRV modulates the comparison behavior of said RFC by adjusting the voltage at said positive input node or the voltage at said negative input node; and said IBC is configured to modulate the voltage at said VBOP in response to the voltage at said VAIP.
地址 Tokyo JP