Floating body memory cell having gates favoring different conductivity type regions

摘要

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

主权项

1. A semiconductor structure, comprising:
a semiconductor substrate comprising a P well region having a first semiconductor fin protruding therefrom and an N well region having a second semiconductor fin protruding therefrom, the first semiconductor fin spaced apart from the second semiconductor fin, wherein the P well region is directly adjacent to the N well region in the semiconductor substrate; a trench isolation layer disposed on the semiconductor substrate between the first and second semiconductor fins, wherein the first and second semiconductor fins extend above the trench isolation layer; a gate dielectric layer disposed on the first and second semiconductor fins and on the trench isolation layer, wherein the gate dielectric layer is continuous between the first and second semiconductor fins; an n type metal gate layer disposed over the gate dielectric layer over the first semiconductor fin but not over the second semiconductor fin, wherein the n type metal gate layer is further disposed on a portion of but not all of the trench isolation layer; and a p type metal gate layer disposed over the gate dielectric layer over the second semiconductor fin, wherein the p type metal gate layer is further disposed over the trench isolation layer and over the n type metal gate layer.