| 发明名称 |
MAP RECYCLING ACCELERATION |
| 摘要 |
An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller generally includes a processor, a cache and a hardware assist circuit. The processor may be configured to initiate a recycle operation by generation of a start index. The cache may be configured to buffer a first level of a map and less than all of a second level of the map. The hardware assist circuit may be configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled. |
| 申请公布号 |
US2016306577(A1) |
申请公布日期 |
2016.10.20 |
| 申请号 |
US201615196363 |
申请日期 |
2016.06.29 |
| 申请人 |
Seagate Technology LLC |
发明人 |
Canepa Timothy;Baryudin Leonid;Hanna Stephen D.;Tang Alex G. |
| 分类号 |
G06F3/06;G06F12/08;G06F12/10 |
主分类号 |
G06F3/06 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a memory configured to store data; and a controller configured to process a plurality of input/output requests to read/write to/from the memory, the controller comprising a processor configured to initiate a recycle operation by generation of a start index, a cache configured to buffer a first level of a map and less than all of a second level of the map, and a hardware assist circuit configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled. |
| 地址 |
Cupertino CA US |
