发明名称 CMOS TRANSISTOR USING HIGH STRESS LINER LAYER
摘要 A MOS transistor structure comprising a gate dielectric layer (30), a gate electrode (40), and source and drain regions (70) are formed in a semiconductor substrate (10). First second and third dielectric layers (110), (120), and (130) are formed over the MOS transistor structure. The second and third dielectric structures (120), (130) are removed leaving a MOS transistor with a stressed channel region resulting in improved channel mobility characteristics.
申请公布号 WO2005112104(A3) 申请公布日期 2006.10.05
申请号 WO2005US16572 申请日期 2005.05.11
申请人 TEXAS INSTRUMENTS INCORPORATED;WU, ZHIQIANG;BU, HAOWEN 发明人 WU, ZHIQIANG;BU, HAOWEN
分类号 H01L21/44;H01L21/31;H01L21/3205;H01L21/336;H01L21/469;H01L29/78 主分类号 H01L21/44
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