| 摘要 |
Devices, methods, and systems for initializing a phased-lock loop (PLL) circuit which prevents or reduces the occurrences of voltage-controlled oscillator (VCO) frequency exceeding a divider's maximum input frequency, thus preventing or reducing at least one cause of lock failure. Disclosed is a PLL circuit having logic circuitry configured to hold a PFD reference-signal input low and provide a divided reference-signal to a PFD feedback-signal input while an initialization signal is asserted. The PLL can be initialized without adding circuitry to a VCO input. By asserting an initialization signal, an input voltage to a voltage-controlled oscillator is attenuated. The initialization signal is adapted to gate inputs to and outputs from the phase-locked loop circuit.
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