发明名称 Sensing amplifier utilizing bit line clamping devices and sensing method thereof
摘要 A sensing amplifier comprising a clamp circuit is provided. The clamp circuit is coupled between a first node and a second node. The clamp circuit comprises a first P-type transistor having a first terminal, a second terminal and a control terminal receiving a first bias signal, the first terminal and the second terminal of the first P-type transistor are coupled to the first node and the second node, respectively, and a sensing current from the memory cell flows into the second node via the first node during a sensing time period.
申请公布号 US9520195(B2) 申请公布日期 2016.12.13
申请号 US201314049257 申请日期 2013.10.09
申请人 MACRONIX INTERNATIONAL CO., LTD. 发明人 Chen Chung-Kuang
分类号 G11C16/06;G11C16/04;G11C7/08;G11C7/06;G11C16/26;G11C16/10 主分类号 G11C16/06
代理机构 McClure, Qualey Rodack, LLP 代理人 McClure, Qualey Rodack, LLP
主权项 1. A sensing amplifier, for sensing data stored in a memory cell of a memory string of which one end is coupled to a third node and another end is coupled to a common source line, comprising: a clamp circuit coupled between a first node and a second node, wherein the clamp circuit comprises a first P-type transistor having a first terminal, a second terminal and a control terminal receiving a first bias signal, the first terminal and the second terminal of the first P-type transistor are coupled to the first node and the second node, respectively, and an isolating transistor, coupled between the third node and the first node; wherein the voltage level of the third node is set to be less than the voltage level of the common source line in a bias setup time period, and the first P-type transistor accordingly clamps the voltage level of the first node to be higher than the voltage level of the second node, such that a sensing current from the memory cell flows into the second node via the first node during a sensing time period subsequent to the bias setup time period.
地址 Hsinchu TW