CHIP-ON-WAFER PACKAGE AND METHOD OF FORMING SAME

摘要

A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past edges of the first device package. The first device package comprises a first die having a first redistribution layer (RDL) disposed on a first substrate, a second die having a second RDL disposed on a second substrate, an isolation material over the first die and extending along sidewalls of the second die, and a conductive via. The first RDL is bonded to the second RDL, and the first die and the second die comprise different lateral dimensions. At least a portion of the conductive via extends from a top surface of the isolation material to contact a first conductive element in the first RDL.

主权项

1. A method comprising:
bonding a die to a wafer, the die having a first redistribution layer (RDL) on a first substrate, the wafer having a second RDL on a second substrate, the first RDL being bonded to the second RDL; forming a first isolation material over the wafer and around the die; and forming a conductive via extending from a top surface of the first isolation material to contact a first conductive element in the first RDL or the second RDL, wherein forming the conductive via comprises:
patterning an opening;extending the opening to expose the first conductive element, wherein extending the opening comprises masking off a portion of the opening; andfilling the opening with a conductive material.