发明名称 ACCELERATING CACHE STATE TRANSFER ON A DIRECTORY-BASED MULTICORE ARCHITECTURE
摘要 Technologies are generally described herein for accelerating a cache state transfer in a multicore processor. The multicore processor may include first, second, and third tiles. The multicore processor may initiate migration of a thread executing on the first core at the first tile from the first tile to the second tile. The multicore processor may determine block addresses of blocks to be transferred from a first cache at the first tile to a second cache at the second tile, and identify that a directory at the third tile corresponds to the block addresses. The multicore processor may update the directory to reflect that the second cache shares the blocks. The multicore processor may transfer the blocks from the first cache in the first tile to the second cache in the second tile effective to complete the migration of the thread from the first tile to the second tile.
申请公布号 US2016210229(A1) 申请公布日期 2016.07.21
申请号 US201615080605 申请日期 2016.03.25
申请人 EMPIRE TECHNOLOGY DEVELOPMENT LLC 发明人 SOLIHIN YAN
分类号 G06F12/08;G06F12/12 主分类号 G06F12/08
代理机构 代理人
主权项 1. A method to accelerate a cache state transfer in a multicore processor, the method comprising: initiating a migration of a thread that executes on a first core at a first tile in the multicore processor from the first tile to a second tile in the multicore processor, wherein the first tile includes the first core and a first directory that maps a first set of block addresses and a first cache, andwherein the second tile includes a second core and a second directory that maps a second set of block addresses and a second cache, determining block addresses of blocks to be transferred from the first cache to the second cache based on the migration of the thread that executes on the first core at the first tile to the second tile in the multicore processor, identifying a third tile in the multicore processor, wherein the third tile includes a third directory that maps a third set of block addresses; updating the third directory to reflect that the second cache shares the blocks by sending a message from the first tile to the third tile; transferring the blocks from the first cache in the first tile to the second cache in the second tile to complete the migration of the thread from the first tile to the second tile; using a transfer status table to maintain first status information on the update of the third directory and second status information on the transfer of the blocks from the first cache to the second cache; and based on the first status information and the second status information maintained in the transfer status table, determining whether to send at least one of an invalidation request or an intervention request from the first tile to the second tile.
地址 WILMINGTON DE US