Input Path Matching in Pipelined Continuous-Time Analog-to-Digital Converters

摘要

System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

主权项

1. A method comprising matching magnitude and phase of a coarse resolution earlier stage sub-analog-to-digital converter path signal in a pipelined continuous-time analog-to-digital converter to magnitude and phase of continuous-time path signal of the pipelined continuous-time analog-to-digital converter using an input delay circuit disposed in the continuous-time signal path of the pipelined continuous-time analog-to-digital converter.