| 摘要 |
The invention relates to a circuit (CL) for reading a pixel matrix (MPA) including, for each column of pixels of said matrix: a plurality of voltage-to-delay converter circuits, receiving as input (E1) a voltage value representing the voltage of a conductor (LC, LC1 - LC3) for reading a respective column (C1 - C3) of pixels (PX) of said matrix, and supplying as output a so-called binary comparison signal (SBC), with switching at one instant in accordance with the input voltage value; a plurality of frequency-multiplying circuits (CMF1 - CMF3), one for each so-called voltage-to-delay converter circuit, receiving as input a so-called primary clock signal (HP) and supplying as output so-called secondary clock signals (HS, HS1 - HS3) with multiple frequencies; and a plurality of binary counters (CBN, CBN1 - CBN3), receiving on a first input (D) one so-called secondary clock signal and on a second input (CLK) one so-called binary comparison signal, and counting at a rate dictated by said secondary clock signal until said binary comparison signal switches. The invention also relates to an image sensor including a pixel matrix, in particular active, and to such a reading circuit. |
