| 发明名称 |
SEMICONDUCTOR ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME |
| 摘要 |
A semiconductor arrangement and a method for manufacturing the same. An arrangement may include a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate. The first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack. The second FinFET includes a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; an isolation section self-aligned to a space defined by the dummy gate spacer. The isolation section electrically isolates the first FinFET from the second FinFET; and an insulation layer disposed under and abutting the isolation section. |
| 申请公布号 |
US2016268392(A1) |
申请公布日期 |
2016.09.15 |
| 申请号 |
US201414411073 |
申请日期 |
2014.01.16 |
| 申请人 |
INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES |
发明人 |
ZHU Huilong |
| 分类号 |
H01L29/66;H01L21/762;H01L29/78 |
主分类号 |
H01L29/66 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor arrangement, comprising:
a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; an isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and an insulation layer disposed under and abutting the isolation section. |
| 地址 |
Beijing CN |
