TWISTED ARRAY DESIGN FOR HIGH SPEED VERTICAL CHANNEL 3D NAND MEMORY

摘要

Roughly described, a memory device has a multilevel stack of conductive layers. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. SSLs run above the conductive layers, each intersection of a pillar and an SSL defining a respective select gate of the pillar. Bit lines run above the SSLs. The pillars are arranged on a regular grid which is rotated relative to the bit lines. The grid may have a square, rectangle or diamond-shaped unit cell, and may be rotated relative to the bit lines by an angle θ where tan(θ)=±X/Y, where X and Y are co-prime integers. The SSLs may be made wide enough so as to intersect two pillars on one side of the unit cell, or all pillars of the cell, or sufficiently wide as to intersect pillars in two or more non-adjacent cells.

主权项

1. A memory device on a substrate, comprising:
a stack of conductive layers, each of the layers being oriented parallel to the substrate; a plurality of parallel bit line conductors parallel to the substrate; a plurality of pillars oriented orthogonally to the substrate; and a plurality of memory cells located at cross-points between the pillars and the conductive layers, wherein the pillars in the plurality of pillars are arranged on a regular grid, the regular grid having a unit cell of four of the pillars A, B, C and D located at vertices of a parallelogram, pillar B being a pillar which is nearest to pillar A in the grid, and pillar D being a pillar which is non-collinear with pillars A and B, wherein the plurality of bit line conductors are orthogonal to a direction from pillar A to pillar D, wherein pillars B and C share one of the bit lines, and wherein a center-to-center distance between pillar A and pillar B is not equal to a center-to-center distance between pillar A and pillar D.