METHOD OF FORMING SUPRA LOW THRESHOLD DEVICES

摘要

A semiconductor device and a method for making the semiconductor device are provided. The semiconductor device includes a non-volatile memory cell having a gate dielectric and formed in a non-volatile memory well region; a first transistor type formed using a first gate oxide and formed in a first transistor well region; a second transistor type formed using a second gate oxide and formed in a second transistor well region; and a third transistor type formed using a third gate oxide and formed in a third transistor well region. The gate dielectric and the first and second gate oxides are formed from the same oxide stack. The first, second, and third transistor types include extension implants formed using a first implant dopant, and the non-volatile memory cell includes extension implants formed using a second implant dopant, where the first and second implant dopants are different.

主权项

1. A method for making a semiconductor device, the method comprising:
forming trench isolation regions in a surface of a substrate to delineate a high voltage transistor region, a first low voltage transistor region, a second low voltage transistor region, and a non-volatile memory region; forming a first oxide layer over the surface of the substrate; etching the first oxide layer from the second low voltage transistor region; forming a second oxide layer over the surface of the substrate; implanting first well regions through the first and second oxide layers in the high voltage transistor region, the first low voltage transistor region, and the non-volatile region; implanting a second well region through the second oxide layer in the second low voltage transistor region, wherein implanting the first well regions and second well region occurs concurrently; selectively etching the first and second oxide layers from the non-volatile memory region, and the first and second low voltage regions; forming a third oxide layer over the surface of the substrate; and forming a transistor gate electrode in each of the high voltage transistor region, the first low voltage transistor region, the second low voltage transistor region, and the non-volatile memory region.