发明名称 |
DOUBLE ASPECT RATIO TRAPPING |
摘要 |
A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant. A plurality of first semiconductor-containing pillar structures of a second semiconductor material having a second lattice constant that is greater than the first lattice constant extend upwards from a surface of the semiconductor substrate portion. A plurality of second semiconductor-containing pillar structures of a third semiconductor material having a third lattice constant that is greater than the first lattice constant extend upwards from another surface of the semiconductor substrate portion. A spacer separates each first semiconductor-containing pillar structure from each second semiconductor-containing pillar structure. Each second semiconductor-containing pillar structure has a width that is different from a width of each first semiconductor-containing pillar structure. |
申请公布号 |
US2016268126(A1) |
申请公布日期 |
2016.09.15 |
申请号 |
US201615162221 |
申请日期 |
2016.05.23 |
申请人 |
International Business Machines Corporation |
发明人 |
Cheng Kangguo;Doris Bruce B.;Khakifirooz Ali;Reznicek Alexander |
分类号 |
H01L21/02;H01L21/762;H01L29/06;H01L29/165;H01L29/267;H01L21/311 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
1. A method of forming a semiconductor structure, said method comprising:
providing a semiconductor substrate comprising a first semiconductor material of a first lattice constant and containing a plurality of sacrificial trench isolation structures therein; forming a plurality of first semiconductor-containing pillar structures comprising a second semiconductor material having a second lattice constant that is greater than said first lattice constant adjacent each sacrificial trench isolation structure and extending upwards from a first sub-surface of said semiconductor substrate; forming a dielectric cap portion on a topmost surface of each first semiconductor-containing pillar structure, wherein a topmost surface of each dielectric cap portion is coplanar with a topmost surface of each sacrificial trench isolation structure of said plurality of sacrificial trench isolation structures; removing each sacrificial trench isolation structure of said plurality of sacrificial trench isolation structures to expose a second sub-surface of said semiconductor substrate; forming a dielectric spacer along sidewall surfaces of each first semiconductor-containing pillar structure and on a portion of said second sub-surface of said semiconductor substrate; and forming a plurality of second semiconductor-containing pillar structures comprising a third semiconductor material having a third lattice constant that is greater than said first lattice constant adjacent said dielectric spacer and on another portion of said second sub-surface of said semiconductor substrate, wherein each of said second semiconductor-containing pillar structures has a width that is different from a width of each of said first semiconductor-containing pillar structures. |
地址 |
Armonk NY US |