发明名称 MANUFACTURING METHOD FOR INTEGRATED CIRCUIT, CONFIGURATION MANUFACTURING INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a manufacturing method for an integrated circuit forming contacts connecting an upper layer and a lower layer at pitches among centers, smaller than the resolution limit of a lithography. <P>SOLUTION: The structures 11 of upper layers 1 and the structures 25 of lower layers 2 manufactured at a standard resolution are connected by the two contacts 31 and 32 mutually separated at intervals shorter than the resolution limit (a sub-lithographic) of the lithography. First masks 6 having lattice type regular patterns in first opening sections (holes) 61 are manufactured by using a double patterning technique for forming the contacts 3 for the sub-lithographic. The contacts containing the contacts 31 and 32 are manufactured by selecting any number of the first opening sections 61 in second masks (not shown) having the standard resolution are manufactured in addition to the first masks. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009049420(A) 申请公布日期 2009.03.05
申请号 JP20080214500 申请日期 2008.08.22
申请人 QIMONDA AG 发明人 MEIER STEFAN DR;WEIS ROLF;LUDWIG BURKHARD;NOELSCHER CHRISTOPH
分类号 H01L21/768;H01L21/027 主分类号 H01L21/768
代理机构 代理人
主权项
地址