发明名称 Rise and fall balancing circuit for tri-state inverters
摘要 Disclosed are various embodiments for adjusting both the rise and fall or both of an output pulse in an inverter circuit so that the output pulse has a length that matches the length of the input pulse. Stages of transistors having various sizes can be activated in both a pull-up circuit, a pull-down circuit or both to adjust the rise time and/or fall time of the output pulse.
申请公布号 US2006284658(A1) 申请公布日期 2006.12.21
申请号 US20050157299 申请日期 2005.06.20
申请人 WRIGHT BRADLEY J 发明人 WRIGHT BRADLEY J.
分类号 H03B1/00 主分类号 H03B1/00
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