发明名称 CLOCK SIGNAL GENERATING CIRCUIT, AND CLOCK SIGNAL GENERATING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To stably generate a clock signal even in a case where any one of or all reference signals of a plurality of systems are interrupted. <P>SOLUTION: An interruption detection section 2-A, 2-B is adapted to detect interruption of a reference signal A of an active system, interruption of a reference signal B of a reserve system and when interruption is detected, an interruption detecting signal is outputted to a control section 8. When an interruption detecting signal from the interruption detection section 2-A is received, the control section 8 switches derivation of an input switching section 1 to the reference signal B. When an interruption detecting signal from the interruption detecting section 2-B is then notified, updating of a held voltage of a control voltage holding section 6 is stopped, and the derivation of the switching section 7 is switched from a control voltage generated by a control voltage generating section 5 to a held voltage held in the control voltage holding section 6. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009021876(A) 申请公布日期 2009.01.29
申请号 JP20070183613 申请日期 2007.07.12
申请人 TOSHIBA CORP 发明人 OTSUKA KUNIAKI
分类号 H03L7/14;H03L7/08;H03L7/095 主分类号 H03L7/14
代理机构 代理人
主权项
地址