发明名称 |
Underlayer process for high O3/TEOS interlayer dielectric deposition |
摘要 |
A underlayer process for high O3/TEOS interlayer dielectric deposition is disclosed. First, a layer of metal pattern is defined on a semiconductor substrate, then a layer of dielectric underlayer is deposited, next, a high O3/TEOS interlayer dielectric is formed to achieve planarization. The key point of this process is to apply materials with higher refraction index than conventional PE-TEOS for forming interlayer dielectric underlayer. The mentioned material can be PE-SiH4 with a constant or decreasing refraction index with the distance from the semiconductor substrate. The underlayer can also be bi-layer structure consisting of high refraction index bottom layer and low refraction index surface layer. This invention can effectively suppress the problem caused from high surface sensitivity of O3/TEOS, and improve the quality of interlayer dielectric planarization process dramatically.
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申请公布号 |
US6025263(A) |
申请公布日期 |
2000.02.15 |
申请号 |
US19970927287 |
申请日期 |
1997.09.11 |
申请人 |
NANYA TECHNOLOGY CORPORATION |
发明人 |
TSAI, HSIN-CHUAN;LIN, CHUNG-MIN |
分类号 |
H01L21/316;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/316 |
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