| 摘要 |
<p>A circuit for decoding a bi-phase BPSK signal, said bi-phase BPSK signal including a plurality of continuous half bit signals and a plurality of carrier pulse signals in synchronization with the plurality of half bit signals, a cycle of said plurality of carrier pulse signals being shorter than a cycle of said plurality of half bit signals, two continuous half bit signals constituting a 1-bit data signal, and said 1-bit data signal being constituted of two half bit signals different in logic from each other, comprising:
a clock reproducing circuit (2) reproducing a plurality of clock pulse signals in synchronization with respective said plurality of half bit signals;
a clock extracting circuit (45) extracting each clock pulse signal corresponding to one of the two half bit signals constituting the 1-bit data signal, from the plurality of clock pulse signals reproduced by said clock reproducing circuit;
a carrier extracting circuit (50) extracting a carrier pulse signal delayed in time from each clock pulse signal extracted by said clock extracting circuit;
a carrier delay circuit (6) delaying the carrier pulse signal extracted by said carrier extracting circuit by one cycle of said plurality of half bit signals; and
a converting circuit (8) converting said plurality of half bit signals to a digital signal, using an output signal from said carrier extracting circuit and an output signal from said carrier delay circuit as a sampling clock signal.
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