INTEGRATED CIRCUIT HAVING MULTIPLE IDENTIFIED IDENTICAL BLOCKS

摘要

An integrated circuit comprising N adjacent identical blocks indexed by index j, a current block connected to preceding and following blocks, each comprising identification circuits comprises: N ordered inputs indexed i, connected to N outputs of the preceding block of same index; and N ordered outputs indexed i, connected to N inputs of the following block of same index; each input for i≠N of the current block connected by routing line indexed to output i+1 of the current block; last input N of the current block not connected to output of the current block; and first output 1 of the current block not connected to input of the current block; each block comprising: a connection pad; and N logic gates indexed i, each gate comprising first and second inputs and an output, N buses indexed i comprising a line through N blocks, and connected to output of a logic gate.

主权项

1. An integrated circuit comprising a plurality of N adjacent identical blocks indexed by an index j, a current block being connected to a preceding block and to a following block, each block comprising an identification circuit comprising:
N ordered inputs indexed i, which inputs are connected to the N outputs of the preceding block of same index; and N ordered outputs indexed i, which outputs are connected to the N inputs of the following block of same index; each input i for i≠N of the current block is connected by a routing line indexed i to the output i+1 of the current block; a last input N of the current block is not connected to any output of said current block; and a first output 1 of the current block is not connected to any input of said current block; each block further comprising:
at least one connection pad; andN logic gates indexed i, each logic gate comprising a first input, a second input and an output,N buses indexed i each comprising a line running through all the N blocks, each bus being connected to the output of a single logic gate, the connection pad being coupled to the buses via the identification circuit and the logic gates so that:
all the first inputs of the logic gates are connected to the connection pad,each second input of a logic gate is connected to a single routing line of the identification circuit.