发明名称 |
DEVICE AND METHOD FOR COMPENSATING TIMING OF DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To provide a memory element which controls timing in transmission and reception of signals between peripheral equipment and itself to stabilize the operation. SOLUTION: An electronic device with device timing restriction includes a set of connection parts which are connected to an interconnection structure which conveys raw and column commands. A memory core stores data. A memory interface is connected to the set of connection parts and the memory core. The memory interface is provided with a circuit which generates memory core timing signals on the basis of row commands and column commands. A memory interface circuit includes individual delay elements which adjust the timing of selected timing signals of the memory core timing signals. COPYRIGHT: (C)2008,JPO&INPIT
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申请公布号 |
JP2008210502(A) |
申请公布日期 |
2008.09.11 |
申请号 |
JP20080024238 |
申请日期 |
2008.02.04 |
申请人 |
RAMBUS INC |
发明人 |
WARE FREDERICK A;BARTH RICHARD M;STARK DONALD C;HAMPEL CRAIG E;TSERN ELY K;ABHYANKAR ABHIJIT M |
分类号 |
G11C11/407;G11C11/409;G06F12/00;G06F13/42;G11C7/10;G11C7/22;G11C11/401;G11C11/4076 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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