发明名称 METHOD AND DEVICE FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To solve the problem that cell arrangement takes place near an error object in improving timing correction by cell insertion, but it is hard to automatically perform cell arrangement which secures both timing and wiring property. SOLUTION: The movement degree of the cell is weighted in a weighting determination step by defining timing information, connection information, and physical information as input information. Then, the movable range of the cell is determined in a movable range determination step, thereby determining the presence or absence of cell arrangeable area. Processing proceeds to a cell movable area enlargement step or a cell arrangement area securing step, based on presence or absence of the cell arrangeable range. Then, the cell is automatically and optimally arranged. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009020575(A) 申请公布日期 2009.01.29
申请号 JP20070180891 申请日期 2007.07.10
申请人 PANASONIC CORP 发明人 YOSHIMURA MASAHIRO;IINUMA NORIKO;KYOTANI MUNEAKI;NAKANISHI RYO;SHIOKAWA TETSUJI;NISHIOKA AKIRA
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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