SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE

摘要

A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure that includes two dielectric layers. The first dielectric layer has an embedded electrically conductive structure. A second dielectric layer is located above the first dielectric layer. The second dielectric layer and the first dielectric layer have a segment of a dielectric capping layer and a segment of a metal capping layer located between them. The segment of the dielectric capping layer is horizontally planar with the segment of the metal capping layer. The segment of metal capping layer covers and abuts at least a portion of a top surface of the first electrically conductive structure. The method includes forming an opening in the second dielectric layer and the metal capping layer that exposes at least a portion of the first electrically conductive structure and a portion of the dielectric capping layer.

主权项

1. A method of fabricating a semiconductor interconnect structure, the method comprising:
providing a semiconductor structure including a first dielectric layer having a first electrically conductive structure embedded therein, a second dielectric layer located above the first dielectric layer, the second dielectric layer and the first dielectric layer having a segment of a dielectric capping layer and a segment of a metal capping layer located therebetween such that the segment of the dielectric capping layer is horizontally planar with the segment of the metal capping layer, the segment of metal capping layer covers and abuts at least a portion of a top surface of the first electrically conductive structure; and forming an opening in the second dielectric layer and the metal capping layer, thereby exposing at least a portion of the first electrically conductive structure and a portion of the dielectric capping layer.