MULTI-BANK MEMORY WITH LINE TRACKING LOOP

摘要

In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.

主权项

1. A circuit, comprising:
a plurality of memory banks arranged in a plurality of rows and a plurality of columns of memory building blocks, each of the plurality of memory banks comprising at least one memory cell; a column line tracking loop that has a first end and a second end and traverses at least a portion of the plurality of rows, and/or a row line tracking loop that has a first end and a second end and traverses at least a portion of the plurality of columns; and a tracking circuit configured to receive a first edge of a first signal, cause the first edge of the first signal to be propagated from the first end to the second end of the column line tracking loop and/or from the first end to the second end of the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal, the first signal being associated with accessing of the plurality of memory banks.