| 摘要 |
PROBLEM TO BE SOLVED: To reduce the power consumption, the dimension and the cost by efficiently executing a process for delaying a received signal. SOLUTION: A selective adding circuit 7a distributes a plurality of received signals into groups respectively, adds the received signals for every group and acquires group sum signals for every group. After delaying the group sum signals by different amounts of delay respectively according to the respective groups, a digital delay adder 7p adds the group sum signals to acquire a single delay sum signal. COPYRIGHT: (C)2009,JPO&INPIT
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