TECHNIQUES FOR MULTIPLE GATE WORKFUNCTIONS FOR A NANOWIRE CMOS TECHNOLOGY

摘要

In one aspect, a method of forming a CMOS device with multiple transistors having different Vt's is provided which includes: forming nanowires and pads on a wafer, wherein the nanowires are suspended at varying heights above an oxide layer of the wafer; and forming gate stacks of the transistors at least partially surrounding portions of each of the nanowires by: i) depositing a conformal gate dielectric around the nanowires and on the wafer beneath the nanowires; ii) depositing a conformal workfunction metal on the conformal gate dielectric around the nanowires and on the wafer beneath the nanowires, wherein an amount of the conformal workfunction metal deposited around the nanowires is varied based on the varying heights at which the nanowires are suspended over the oxide layer; and iii) depositing a conformal poly-silicon layer on the conformal workfunction metal around the nanowires and on the wafer beneath the nanowires.

主权项

1. A method of forming a complementary metal oxide semiconductor (CMOS) device comprising multiple nanowire-based transistors having different threshold voltages, the method comprising the steps of:
providing a wafer comprising an oxide layer on a substrate; forming nanowires and pads on the wafer, wherein the pads are attached to opposite ends of the nanowires and anchor the nanowires to the wafer, and wherein the nanowires are suspended at varying heights above the oxide layer; and forming gate stacks of the nanowire-based transistors at least partially surrounding portions of each of the nanowires by: i) depositing a conformal gate dielectric both around the nanowires and on the wafer beneath the nanowires; ii) depositing a conformal workfunction metal on the conformal gate dielectric both around the nanowires and on the wafer beneath the nanowires, wherein an amount of the conformal workfunction metal deposited around the nanowires is varied based on the varying heights at which the nanowires are suspended over the oxide layer; and iii) depositing a conformal poly-silicon layer on the conformal workfunction metal both around the nanowires and on the wafer beneath the nanowires, wherein the portions of the nanowires at least partially surrounded by the gate stacks serve as channel regions of the nanowire-based transistors, wherein portions of the nanowires extending out from the gate stacks and the pads serve as source and drain regions of the nanowire-based transistors, and wherein the nanowire-based transistors have different threshold voltages based on the varied amount of the conformal workfunction metal deposited around the nanowires.