发明名称 Data Processing Architectures
摘要 A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.
申请公布号 US2007220232(A1) 申请公布日期 2007.09.20
申请号 US20070752299 申请日期 2007.05.23
申请人 发明人 RHOADES JOHN;CAMERON KEN;WINSER PAUL;MCCONNELL RAY;FAULDS GORDON;MCINTOSH-SMITH SIMON;SPENCER ANTHONY;BOND JEFF;DEJAEGHER MATTHIAS;HALAMISH DANNY;PANESAR GAJINDER
分类号 G06F13/36;G06F15/00;G06F1/10;G06F17/50;H04L12/28;H04L12/54;H04L12/56 主分类号 G06F13/36
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