发明名称 |
Verfahren und Anordung zur Verminderung einer Taktverschiebung zwischen zwei Signalen |
摘要 |
An electronic integrated circuit includes a first signal (A1) generated by a first source block (10) and a second signal (B1) generated by a second source block (12). A variable delay circuit (18) detects a delay between said first and second signals in calibration mode and applies the delay to the first signal during normal operation of the circuit. A fixed delay buffer (32) may be used to apply a delay to the second signal to compensate for known delays associated with the variable delay circuit (18). <IMAGE> |
申请公布号 |
DE60319664(D1) |
申请公布日期 |
2008.04.24 |
申请号 |
DE2003619664 |
申请日期 |
2003.01.02 |
申请人 |
TEXAS INSTRUMENTS INC. |
发明人 |
JIGUET, JEAN-CHRISTOPHE;COPPOLA, FRANCESCO |
分类号 |
H03K5/13;G06F1/10;H03K5/135;H03L7/081;H04J3/04;H04L7/033;H04L7/10 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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