发明名称 |
METHOD AND DEVICE FOR PROGRAMMING A FPGA |
摘要 |
A method of programming a FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprises the steps of: providing a high-level configuration file containing: first data defining a set of macrocells and their relative positions; second data defining a configuration of the hardware blocks of the macrocells; and third data defining interconnections between the macrocells; wherein said high-level configuration file contains neither data defining an absolute position of the macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; converting said high-level configuration file into a bitstream file; and uploading the bitstream file into the FPGA. A semiconductor chip comprising a FPGA and a device configured for programming the FPGA are provided. |
申请公布号 |
US2016342722(A1) |
申请公布日期 |
2016.11.24 |
申请号 |
US201515110064 |
申请日期 |
2015.01.08 |
申请人 |
UNIVERSITE DE RENNES 1 ;INRIA |
发明人 |
SENTIEYS Olivier;PILLEMENT Sébastien;HURIAUX Christophe;COURTAY Antoine |
分类号 |
G06F17/50;G06F15/78 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A method of programming a FPGA, wherein said FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprising the steps of:
a) providing a high-level configuration file containing:
first data defining a set of macrocells and their relative positions;second data defining a configuration of the hardware blocks of said macrocells; andthird data defining interconnections between said macrocells; wherein said high-level configuration file contains neither data defining an absolute position of said macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; b) converting said high-level configuration file into a bitstream file; and c) uploading said bitstream file into the FPGA. |
地址 |
RENNES Cedex FR |