发明名称 PSEUDORANDOM BIT SEQUENCES IN AN INTERCONNECT
摘要 In an example, a linear feedback shift register (LFSR) provides pseudorandom bit sequences (PRBSs) to an interconnect for training, testing, and scrambling purposes. The interconnect may include a state machine, with states including LOOPBACK, CENTERING, RECENTERING, and ACTIVE states, among others. The interconnect is permitted to move from “CENTERING” to “LOOPBACK” via a sideband signal. In LOOPBACK, CENTERING, and RECENTERING, PRBSs are used for training and testing purposes to electrically characterize and test the interconnect, and to locate a midpoint for a reference voltage Vref. A unique, noncorrelated PRBS is provided to each lane, calculated using one common output bit.
申请公布号 US2016285624(A1) 申请公布日期 2016.09.29
申请号 US201514669743 申请日期 2015.03.26
申请人 Intel Corporation 发明人 Wagh Mahesh;Wu Zuoguo;Iyer Venkatraman
分类号 H04L9/06 主分类号 H04L9/06
代理机构 代理人
主权项 1. An interconnect apparatus comprising: n data lanes; and a pseudorandom bit sequence (PRBS) generator, the PRBS generator to provide a separate and noncorrelated PRBS to each of the n data lanes comprising at least a victim lane and an aggressor lane.
地址 Santa Clara CA US