SEMICONDUCTOR DEVICE

摘要

The present invention provides a technique for further improving the processing efficiency in accordance with the setting of the number of waits in a semiconductor device that arbitrates data transfer through a bus between a plurality of bus masters and a plurality of bus slaves.;A semiconductor device includes a clock supplying unit that independently supplies clocks to a plurality of bus slaves and a plurality of bus masters. The number of waits in accordance with an operating frequency can be set for each bus slave such as a memory. As the setting of the number of waits becomes smaller, the clock supplying unit improves the operating frequency by controlling a phase difference between the clocks supplied to the bus masters and the bus slaves in accordance with the number of waits set for each bus slave.

主权项

1. A semiconductor device comprising:
a plurality of bus slaves; a plurality of bus masters that accesses the bus slaves through a bus; and a clock supplying unit that supplies clocks to the bus slaves and the bus masters, wherein the number of waits in accordance with an operating frequency can be set for at least any one of the bus slaves, and wherein the clock supplying unit is configured to control a phase difference between the clocks supplied to the bus masters and the bus slaves in accordance with the number of waits set for each bus slave.