BIAS CIRCUITRY FOR DEPLETION MODE AMPLIFIERS

摘要

A circuit (10) having an amplifier (11), comprising: a depletion mode transistor (Q1) having a source electrode coupled to a reference potential; a drain electrode coupled to a potential (VDD) more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit (10) includes a bias circuit (12), comprising: a current source; and biasing circuitry coupled to the current source and between the potential (VDD) more positive than the reference potential and a potential (-VSS) more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.