Apparatus for Generating Clock Signals having a PLL part and Synthesizer Part with Programmable Output Dividers

摘要

A clock signal generator responsive to synchronization pulses to perform actions has a phase locked loop (PLL) part including a digitally controlled oscillator (DCO) and an output driver coupled to the DCO, and a synthesizer part including a frequency synthesizer responsive to frequency and phase information from the DCO to generate a synthesized clock and programmable output dividers for generating output clocks from the synthesized clock. An interface establishes communication between the PLL part and the synthesizer part. The output driver is programmed to compute a phase offset required to align a selected output divider with the phase of the DCO and transmit the computed offset to the selected output divider over said interface for application to said selected output divider upon the occurrence of a synchronization pulse.

主权项

1. An apparatus for generating clock signals, said apparatus being responsive to synchronization pulses to perform actions and comprising:
a phase locked loop (PLL) part including a digitally controlled oscillator (DCO) and an output driver coupled to said DCO; a synthesizer part including a frequency synthesizer responsive to frequency and phase information from the DCO to generate a synthesized clock and programmable output dividers for generating output clocks from said synthesized clock; and an interface establishing communication between said PLL part and said synthesizer part; and said output driver being programmed to compute a phase offset required to align a selected output divider with the phase of the DCO and transmit the computed offset to the selected output divider over said interface for application to said selected output divider upon the occurrence of a synchronization pulse.