Standby Mode State Retention Logic Circuits

摘要

A retention mode sequential logic circuit has no balloon latch, and all its P-channel transistors are disposed in a single N-well. In one example, the circuit is a retention flip-flop that has an active high retention signal input and an active low reset input. In another example, the circuit is a retention flip-flop that has an active low retention signal input and an active low reset input. In a multi-bit retention register example, one common clock and reset signal generation logic circuit drives multiple pairs of latches. Each retention mode logic circuit described has a low transistor count, is implemented with a single N-well, exhibits low retention mode power consumption, is not responsive to a reset signal in the retention mode, and has a fast response time when coming out of retention mode operation.

主权项

1. A state retention logic circuit comprising:
a first inverter coupled to a clock signal input node CK and outputting a second clock signal CN; a second inverter coupled to the first inverter and outputting a first clock signal C; a pulldown N-channel transistor coupled to a ground node, the clock signal input node CK, and a retention signal input node RT; a gate circuit coupled to the retention signal input node RT and a reset signal input node RN, and outputting a reset signal RS; a first latch receiving a data signal from a first data input node D1, wherein the first latch is clocked by the first clock signal C and the second clock signal CN; and a second latch coupled to the first latch, and outputting a data signal, wherein the second latch is clocked by the first clock signal C and the second clock signal CN, wherein the second latch further comprises:
a gate having a first input lead and an output lead; anda tri-statable feedback element having an input lead and an output lead, wherein the input lead of the tri-statable feedback element is coupled to the output lead of the gate, wherein the output lead of the tri-statable feedback element is coupled to the first input lead of the gate, and wherein the tri-statable feedback element is enabled and disabled by the first clock signal C and the second clock signal CN, wherein the first inverter, the gate of the second latch, and the tri-statable feedback element of the second latch are all powered by a second supply voltage VSUP2, and wherein the second inverter and the first latch are powered by a first supply voltage VSUP1.