发明名称
摘要 PROBLEM TO BE SOLVED: To provide a circuit for reducing noise due to inter-code interference that performs noise reduction processing at high speed. SOLUTION: A forward filter 10 predicts inter-code interference and an adder 20 calculates a forward filter output signal and feedback filter output signals (compensation signals) to whiten noises in a reproduction signal subjected to partial response equalization. Then a Viterbi detector 30 receives the output of the adder 20 to decode it. A feedback filter 40 produces the compensation signals by using path outputs selected depending on comparison results of path metrics. The feedback filter 40 comprises register replacement type shift registers. COPYRIGHT: (C)2004,JPO
申请公布号 JP4061986(B2) 申请公布日期 2008.03.19
申请号 JP20020187338 申请日期 2002.06.27
申请人 发明人
分类号 G06F11/10;G11B20/14;G10L19/00;G10L21/02;G11B5/09;G11B20/10;G11B20/18;H03M13/41;H04L25/03;H04L25/497 主分类号 G06F11/10
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