Master-slave type flip-flop circuit and latch circuit

摘要

A clock input circuit 13 receives power during standby mode and comprises a NAND circuit NAND 0 that controls a clock signal CK using a standby mode signal RET. When the standby mode signal RET is at a low level (in standby mode) clock signals C 01 and C 02 are kept at a high level and low level respectively regardless of the level of the clock signal CK. Further, power continues to be supplied to an FA section in the clock input circuit 13 and to an FB section in a slave latch circuit 12 whereas the power supply to the other circuits is shut off. As a result, the clock signals C 01 and C 02 remain at the high level and low level respectively and data is held by a loop formed by an on-state transfer gate circuit TG 4 and activated inverter circuits INV 5 and INV 6 in the slave latch circuit 12.