发明名称 Software programmable timing architecture
摘要 An apparatus for generating a digital signal pattern may comprises a memory, a program sequencer, first and second circuits, and an event execution unit. The memory may have stored therein a plurality of instructions that, when executed, cause a digital signal pattern to be generated on a plurality of nodes. The program sequencer may be configured to control a sequence in which the plurality of instructions are retrieved from the memory and executed. The first circuit may sequentially step through a plurality of different output states in response to a clock signal. The second circuit may identify an output event when an output state of the first circuit corresponds to an output state identified by retrieved instructions of a particular type. The event execution unit may control states of signals on the plurality of nodes in a manner specified by the retrieved instructions of the particular type in response to the second circuit identifying an output event.
申请公布号 US2008219112(A1) 申请公布日期 2008.09.11
申请号 US20070818449 申请日期 2007.06.14
申请人 ANALOG DEVICES, INC. 发明人 OLOFSSON ANDREAS D.;JACOBS CHRISTOPHER;KETTLE PAUL
分类号 G11B7/00 主分类号 G11B7/00
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