发明名称 V-SHAPED SIGE RECESS VOLUME TRIM FOR IMPROVED DEVICE PERFORMANCE AND LAYOUT DEPENDENCE
摘要 Some embodiments of the present disclosure relates to a method of forming a transistor device having a strained channel and an associated device. In some embodiments, the method is performed by performing a first etch of a substrate to produce a recess having a largest width at an opening along a top surface of the substrate. An etch stop layer is formed by doping a bottom surface of the recess with a dopant. A second etch of the recess is then performed to form a source/drain recess, wherein the etch stop layer resists etching of the second etch. A stress inducing material is formed within the source/drain recess onto the etch stop layer.
申请公布号 US2016254366(A1) 申请公布日期 2016.09.01
申请号 US201615151663 申请日期 2016.05.11
申请人 Taiwan Semiconductor Manufacturing Co., Ltd. 发明人 Chen Chao-Hsuing;Wang Ling-Sung;Lin Chi-Yen
分类号 H01L29/66;H01L29/78;H01L29/16;H01L21/265;H01L21/02;H01L29/165;H01L21/306;H01L29/08 主分类号 H01L29/66
代理机构 代理人
主权项 1. A method of recess formation, comprising: performing a first etch of a substrate to produce a recess having a largest width at an opening along a top surface of the substrate; forming an etch stop layer by doping a bottom surface of the recess with a dopant; performing a second etch of the recess to form a source/drain recess, wherein the etch stop layer resists etching of the second etch; and forming a stress-inducing material on the etch stop layer within the source/drain recess.
地址 Hsin-Chu TW