PLL SYSTEM WITH MASTER AND SLAVE DEVICES

摘要

A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s).

主权项

1. A master phase locked loop device operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), comprising:
at least one digital PLL (DPLL) channel, each including a master digitally controlled oscillator (mDCO) having a higher resolution than said slave digitally controlled oscillators; a master synchronization timer for generating master timing pulses to permit reading phase and frequency information from said mDCO(s); a peripheral interface for sending said read frequency and phase information to said one or more slave devices; and a master synchronization interface for sending said master timing pulses to synchronize a replica synchronization timer in said sDCO(s) that generates slave timing pulses for use in updating said phase and frequency information received at said slave device(s).