Computer architecture with peripherals

摘要

A shared memory computing device that has a system interconnect, an on-chip random access memory (RAM), at least one sub-computing device and a peripheral. The RAM is connected to the system interconnect. Each sub-computing device has: (a) a first local interconnect, (b) an interconnect master connected to a local interconnect of the sub-computing device; and (c) an interconnect bridge; in which the interconnect master is adapted to issue memory transfer requests to the RAM over that bridge. The peripheral comprises a target port which is connected to the first local interconnect of the first of the at least one sub-computing devices; and a first interconnect master port which is adapted to issue memory transfer requests to the RAM. The interconnect master of the first of the at least one sub-computing devices is adapted to issue memory transfer requests to the first peripheral.

主权项

1. A shared memory computing device comprising:
a first system interconnect; an on-chip random access memory store comprising at least one interconnect target port, in which the first interconnect target port is connected to the first system interconnect; at least one sub-computing device, each sub-computing device comprising:
a first local interconnect;a first interconnect master connected to a local interconnect of the sub-computing device;an interconnect bridge comprising two ports, in which:
the first port is connected to the first system interconnect; andthe second port is connected to a local interconnect of the sub-computing device; andin which the first interconnect master is adapted to issue memory transfer requests to the on-chip random access memory store; and a first peripheral, comprising:
a first interconnect target port which is connected to the first local interconnect of the first of the at least one sub-computing devices;a first interconnect master port which is adapted to issue memory transfer requests to the on-chip random access memory store; in which:
the first interconnect master of the first of the at least one sub-computing devices is adapted to issue memory transfer requests to the first peripheral.