DIGITAL FILTER CIRCUIT, RECEIVING CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To shorten a lock time and realize stability of data at the time of locking in a CDR circuit of a receiving circuit.SOLUTION: A phase digital code conversion circuit determines whether or not a phase of an internal clock advances to a serial input signal or retreats, and outputs a first determination code. A determination circuit outputs a second determination code on the basis of a plurality of first determination codes per first period. A gain control code generation part generates a gain control code on the basis of a total sum of the first determination code in the first period. A phase adjustment code generation part gives the gain corresponding to the gain control code to the second determination code, and generates and outputs a phase adjustment code adjusting the phase of internal clock. A proper gain is given to the phase digital code conversion circuit by dynamically changing in accordance with the total sum of the first determination code the gain given to the second determination code.SELECTED DRAWING: Figure 3