| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an asynchronous interface circuit which enables verifiable data transmission and reception between transmitting- and receiving-side blocks, without increasing STA verification and test pattern creation. <P>SOLUTION: In the asynchronous interface circuit interposed in between the transmitting- and receiving-side blocks having respective master clock signals, one block of the transmitting- and receiving-side blocks receives the master clock signal of the other block. When the count value, based on the master clock signal of one-side block which is obtained from the leading or the trailing edge of the received master clock signal agrees with a predetermined value, a block-generating circuit which masks the master clock signal of the one-side block and feeds it to the one-side block is provided. <P>COPYRIGHT: (C)2010,JPO&INPIT |
