| 摘要 |
In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers. |
| 主权项 |
1. A semiconductor device comprising:
a substrate having a memory cell area and a logic area; a first active area and a second active area in the memory cell area on the substrate; a third active area in the logic area on the substrate; an insulating layer on the substrate, the insulating layer configured to cover the first, second and third active areas; a first gate electrode configured to pass through the insulating layer, cover a side surface of the first active area, and cross the first active area, the first gate electrode including,
a first P-work-function metal layer in the first active area,a first capping layer on the first P-work-function metal layer,a first N-work-function metal layer on the first capping layer,a first barrier metal layer on the first N-work-function metal layer, anda first conductive layer on the first barrier metal layer, the first conductive layer having a different material from the first barrier metal layer; a second gate electrode configured to pass through the insulating layer, cover a side surface of the second active area, and cross the second active area, the second gate electrode including,
a second capping layer in the second active area,a second N-work-function metal layer on the second capping layer,a second barrier metal layer on the second N-work-function metal layer, anda second conductive layer on the second barrier metal layer, the second conductive layer having a different material from the second barrier metal layer; and a third gate electrode configured to pass through the insulating layer, cover a side surface of the third active area, and cross the third active area, the third gate electrode having a width smaller than the first gate electrode and the second gate electrode and not having the first and second conductive layers, the third gate electrode including,
a second P-work-function metal layer in the third active area,a third capping layer on the second P-work-function metal layer,a third N-work-function metal layer on the third capping layer, anda third barrier metal layer on the third N-work-function metal layer. |
