Anti-shoot-through automatic multiple feedback gate drive control circuit

摘要

Automatic and robust anti-shoot-through glitch-free operation of half-bridge control pre-driver and power stage circuits have been achieved by using multiple feedback control signals. These feedback signals are taken both from the gates of power devices on high side and low sides and from the gates of one or more devices on both high side and low side that enable power device ON state. No duty cycle limitation is required of the input signal. The control logic uses NAND/NOR RS latches. The solution disclosed can readily be scaled to higher order of feedback loops providing even greater level of robustness.

主权项

1. A system capable of an automatic and robust anti-shoot-through glitch-free operation of half-bridge control pre-driver and power stage circuits using at least two feedback loops from each branch of the half-bridge, comprising:
one input port receiving an input signal; one output port; a high-side branch and a low-side branch arranged in parallel, wherein both branches are connected to the input port, each branch comprising:
a power transistor having a gate controlled by n pre-drivers connected in series, wherein n is an integer number equal or higher than 2;said n pre-drivers driving the power transistor of the correspondent branch; anda number of logic control blocks connected in series enabling to switch to ON state or to switch to OFF state of the power transistor of the correspondent branch via the n pre-drivers of the correspondent branch wherein a first of the number of logic control blocks is connected to the input port and a last logic control block is connected to a first of the n pre-drivers, and wherein the logic blocks comprise either logical NOT AND (NAND) logic gates or NOT OR (NOR) logic gates; wherein both power transistors are connected in series between VDD voltage and ground, wherein a source of the high side power transistor is connected to VDD voltage, a drain of the high side power transistor is connected to a drain of the low side power transistor, the source of the low side power transistor is connected to ground, wherein the drains of both power transistors are connected to the output port, wherein only the drains of the power transistors provide input to the output port, and wherein two or more feedback loops from each branch are implemented from each branch to the logic control blocks of the opposite branch in order to be capable of preventing cross-conduction between both power transistors of the low side and of the high side.