| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce a circuit pattern area, and to increase dimensional accuracy of a hole pattern. <P>SOLUTION: In a pattern design method for a hole pattern, a grid having an interval smaller than the minimum pitch allowed by a design rule of a semiconductor integrated circuit is provided in a pattern figure; and a hole pattern is disposed in a first grid point as an intersection of the grid, while no hole pattern is disposed in a second grid point group in the periphery of the first grid point and adjacent to the first grid point. The number of hole patterns that can be disposed in a third grid point group in the periphery of the second grid point and within a predetermined distance from the first grid point is controlled based on the correspondence data wherein a dimensional error of a resist pattern is associated with the number of hole patterns disposed in the third grid point group. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
