| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory which quickly detects fail bits. <P>SOLUTION: A plurality of memory cells are arranged in rows and columns in a memory cell array 1. The sense amplifier units SAU1-SAUn include sense amplifiers S/A1-S/A8 to detect write completion in the memory cells selected for each row. A plurality of detectors DTU1-DTUn are disposed respectively for the sense amplifier units to form the transfer paths 70 to transfer the potentials according to the detection output signal of each sense amplifier unit, and detect the sense amplifier units at the positions where the transfer paths 70 is discontinued as sense amplifier units containing a write incomplete bit. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
