| 主权项 |
1. A ferroelectric random access memory comprising:
a memory cell matrix constituted by a plurality of 1T1C type memory cells of j rows and k columns (j is an integer of 2 or more and k is an integer of 1 or more), and having j bit lines, k word lines, and k plate lines, said k word lines and said k plate lines being paired with each other, and each of said plurality of 1T1C type memory cells being connected to one of said j bit lines and one pair of said k word lines and said k plate lines; a word line drive circuit which selects either one word line of said k word lines in accordance with a selection signal; a plate line drive circuit which selects one plate line of said k plate lines paired with the selected one word line, and selectively applies one of a first potential and a second potential having a higher potential level than the first potential to said one plate line during a data writing time period; and an equalizing circuit which performs an equalizing process in which the first potential is applied to each of said j bit lines, wherein said plate line drive circuit applies, after said data writing time period, a third potential having a potential level between the first and second potentials to said one plate line, during a predetermined time period including a starting time of said equalizing process. |
