| 摘要 |
A method and a device for sharing a memory through multiple routes are provided to minimize latency in high quality image processing and decrease processing efficiency of a sub processor, and enable a main processor to control the sub processor and transceive data with the sub processor through one bus. The sub processor(320) is controlled by the main processor(310) and is connected to the main processor through one connection bus. A sub memory(325) is equipped with multiple ports and each port is combined with the sub processor through an independent memory bus. At least one of the memory buses is exclusively used by the sub processor to read the data stored in the memory and store the processed data to the sub memory. The sub processor includes an interface(343) for receiving information corresponding to a control signal or the data from the main processor through the connected bus. The data is stored to the sub memory through the memory bus allocated among the memory buses to store the data received from the main processor.
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