| 摘要 |
Disclosed is a phase clock generator. The phase clock generator can include transistors and a buffer. The transistors are connected between a power line and a grounding line and are provided in a form of a 4xN matrix to receive a plurality of phase-delayed signals through their gate terminals. Four transistors can form a unit column between the power line and the grounding line. From ground line to power line, the first two transistors of the unit column provide a pair of NMOS transistors, and the second two transistors provide a pair of PMOS transistors. The buffer is connected to a line, which is provided between the pair of the NMOS transistors and the pair of the PMOS transistors forming the unit column, to transmit a clock signal.
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