发明名称 キャッシュメモリおよびプロセッサシステム
摘要 A cache memory has cache memory circuitry comprising a nonvolatile memory cell to store at least a portion of a data which is stored or is to be stored in a lower-level memory than the cache memory circuitry, a first redundancy code storage comprising a nonvolatile memory cell capable of storing a redundancy code of the data stored in the cache memory circuitry, and a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code.
申请公布号 JP6030085(B2) 申请公布日期 2016.11.24
申请号 JP20140058848 申请日期 2014.03.20
申请人 株式会社東芝 发明人 池上 一隆;藤田 忍;野口 紘希
分类号 G06F11/10;G06F11/14;G06F12/08 主分类号 G06F11/10
代理机构 代理人
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